In recent years, the development of new non-volatile storage devices such as resistance variable type memory (e.g., “ReRAM” (Resistance Random Access Memory)), conductive bridging type memory (e.g., “CBRAM” (Conductive Bridging Random Access Memory)) and the like have become a significant area of research and development. The resistance variable type memory and the conductive bridging type memory utilize a difference in a resistance value between a first state (a “low resistance state”) and a second state (a “high resistance state”) in a layer (a “variable resistance layer”) which has variable resistance characteristics according to an applied voltage level. The variable resistance layer has generally good insulation characteristics, but at some applied voltage level, the layer forms conductive channels (“filaments”) that reduce resistance (i.e., improve conductance) of the layer. The variable resistance layer can also be returned to the original insulating state (high resistance state).
For the resistance variable type memory and the conductive bridging type memory, a cross-point type memory cell array structure is typically adopted as it is viewed as easier to achieve high levels of integration, i.e., a high density of memory cells or elements, using such a structure.
However, when a cross-point type memory cell array structure is used, it will be necessary to carry out a photolithography process and an etching process for each layer of the structure, and thus the manufacturing cost will increase with the number of layers in the cell array. Therefore, a layered-type memory cell array structure that has memory cells of the vertical gate type or memory cells of the vertical channel type have been proposed.
When a layered-type memory cell array structure is used, the layered memory cell array can be formed in batch processing, by first forming the multiple electrode and insulating layers that will constitute the memory cell array, and then etching through the layers to isolate individual memory cells therefrom. This will reduce manufacturing costs of the memory cell array so long as the film layers may be pattern etched into individual cells without creating defects or shorts in the resulting stack.
However, when a layered-type memory cell array structure is formed by pattern etching, typically using a reactive ion etch, the sidewalls of the etched trenches or vias are typically tapered, where the uppermost portion of the trench or via is larger than the lowermost portion of the trench or via. Sidewall tapering can be the result of imperfect masking (edges of a masking feature may degrade during etching) or imperfect anisotropy of the etch process. In the manufacture of the memory cell, after etching of the trenches or vias to isolate individual stacks or pillars of memory cells, a variable resistance layer is deposited over the sidewalls of the stack, and, over the base of the trench or via. Thereafter, the portion of the variable resistance layer on the base of the trench or via must be removed, to avoid shorting between adjacent cells, again using a reactive ion etch process. But, because the sidewalls of the trench or via are tapered and are wider at the top of the feature as compared to the base of the feature, the portion of the variable resistance layer on the lower part of the feature, i.e., closer to the base, is etched away faster than that at the top, resulting in a thinner, or even no, variable resistance layer at the bottom of the feature, and a thicker layer at the top of the structure. If some portions of the variable resistance layer formed at the lower portion of the layered body are removed, the thickness of the variable resistance layer at the upper portion and the lower portion of the layered body will be different, and there is a danger of variation occurring in the memory characteristics of the resultant memory cells.